AMD Posts GCC Compiler Patches For AVX10V1AUX ISA Support

Following their recent AVX10_V2_AUX support for GCC as part of the bring-up for the AI Compute Extensions "ACE" in GCC 17, AMD compiler engineers this week posted the initial patches for enabling the AVX10V1AUX ISA support. AVX10V1AUX is the auxiliary updates for AVX10.1 also as part of the ACE initiative. AVX10V1AUX isn't as in-depth as AVX10_V2_AUX with the compressed AI data format types but does carry some transitionary instructions that map onto the AVX10.2 structure. The AMD patches to GCC for the AVX10V1AUX ISA support add the infrastructure plus share some built-ins and patterns from AVX10.2 along with VNNINT8 and VNNIINT16 for AVX10V1AUX usage. The CONVERT intrinsics from AVX10.2 are also carried over for AVX10V1AUX. With the patches, -mavx10v1aux is used for enabling the support on capable yet-to-be-released processors from Intel and AMD. The AVX10V1AUX patches for the GNU Compiler Collection are out for review on the gcc-patches mailing list.