Intel Posts Initial GCC Compiler Code For Razor Lake & Coral Rapids

One of the consistent wonderful praise I have for Intel over the past 22+ years of covering the Linux hardware scene has been their upstreaming of new CPU targets into the open-source compilers like GCC well ahead of product launches. Particularly with GCC on an annual feature release cycle and not being quickly picked up by new Linux distribution releases, Intel upstreaming their new CPU targets and ISA features at times years in advance of product releases has helped ensure smooth compiler ecosystem support by the time their products ship. The latest example, today they posted their patches providing new ISA features and enabling for both Coral Rapids and Razor Lake processors. Since late 2024 there was GCC support for Diamond Rapids as the next-generation Xeon processors launching in 2027. Now even before Diamond Rapids is shipping, the initial Coral Rapids support is now in patch form and will be presumably merged in time for the GCC 17.1 compiler release due out in early 2027. Similarly, Intel Nova Lake support came to GCC 16 last year and Razor Lake as its successor is out today with these new GCC patches. Coral Rapids and Razor Lake aren't shipping until 2028 at least but this very early GCC enablement should be in place for GCC 17 and work its way out as the default compiler in various Linux distributions by the time these processors are shipping to customers a year later. Kudos to Intel for again delivering their compiler patches so early. The Razor Lake patch confirms that Razor Lake has all the same ISA features as Nova Lake. So not particularly interesting there from the ISA perspective. The patch bringing up Coral Rapids is more interesting and confirms the ISA capabilities of: "Intel Coral Rapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16, PREFETCHI, AMX-COMPLEX, AVX10.1, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16, AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2, APX_F, AMX-AVX512, AMX-FP8, AMX-TF32, MOVRS, AMX-MOVRS, AVX10_VPMLDSABFLYDQ instruction set support." AVX10_VPMLDSABFLYDQ being one of the main ISA differences for Coral Rapids over Diamond Rapids. VPMLDSABFLYDQ is for Packed ML-DSA Butterfly Operations. A separate patch today adds the AVX10_VPMLDSABFLYDQ intrinsics for GCC. Interestingly at least for now Coral Rapids is AVX10.2 confirmed and not AVX10.3. AVX10.3 specs were recently posted but looks like that won't be here for Coral Rapids in 2028 nor ACEv2 as presumably the Coral Rapids design was too far along by the time those new specs solidified. Today also marked an updated patch series for GCC of that AVX10.3 support and also now includes AVX10_BMM support that was left out of the original version.