Chinese firm targets 8000 Megatransfer per second memory speeds with new chip controller

As artificial intelligence models become larger and cloud platforms process ever-growing amounts of data, one challenge is becoming increasingly difficult to ignore, which is memory. Today’s servers can only use the memory physically attached to their processors, creating hard limits on how much data they can handle efficiently. “AI and data center workloads are driving continuous evolution of system architecture, making memory a key factor in performance and scalability,” Amit Goel, an expert in enterprise AI solutions from AMD, said. Expanding memory often means adding more servers, increasing costs while leaving valuable resources underused. Montage Technology says it has taken an important step toward solving this problem with the trial production of what it describes as Compute Express Link (CXL) 3.2 Memory eXpander Controller (MXC) chip. In simple terms, the chip acts as a bridge between a processor and external memory, allowing servers to tap into much larger memory pools instead of relying only on the memory installed next to the CPU. That could make future AI infrastructure more flexible, scalable, and efficient. Breaking the memory wall Modern AI applications, including large language models and scientific simulations, require enormous amounts of fast memory to store data and perform calculations. While processors have become increasingly powerful, memory capacity has struggled to keep pace because conventional server designs tightly couple memory to the CPU. “AI, next-generation cloud systems, and today’s industry economics are reshaping server memory architecture and driving demand for CXL,” Debendra Das Sharma, an expert in computing technology and chief I/O architect at Intel, said. The industry has been working to address this limitation through Compute Express Link (CXL), an open standard that enables processors, memory, and accelerators to communicate over high-speed PCI Express connections. Earlier CXL products demonstrated memory expansion, but Montage’s controller is built around the latest CXL 3.2 specification, adding support for more advanced features such as memory pooling and tiered memory architectures. Inside the new controller Rather than storing data itself, the MXC chip acts as an intelligent bridge between a server’s processor and external DDR5 memory. The controller complies with CXL Type 3, supporting both CXL.mem and CXL.io protocols, alongside PCIe 6.x, allowing data transfer speeds of up to 64 GT/s (Gigatransfer per second). It integrates two DDR5 memory controllers that support memory running at up to 8000 MT/s (Megatransfer per second). When a processor requests data, the chip instantly converts CXL memory requests into DDR5 commands, retrieves the required information, and sends it back in real time. This allows servers to access much larger memory capacities than would normally be possible. The chip also integrates PCIe 6.x and DDR5 physical interfaces, dual RISC-V processor subsystems, and management interfaces. It supports multiple deployment formats, including PCIe add-in cards (AICs) and Enterprise and Datacenter Standard Form Factor (EDSFF) modules, enabling memory expansion, resource pooling, and tiered memory systems that can use hardware more efficiently across demanding workloads. A full package, but real-world testing remains Montage says the controller has already been integrated into next-generation CXL products from Samsung and SK hynix, with initial validation completed. The company also designed the chip to work with leading server platforms based on Intel Xeon and AMD EPYC processors, improving compatibility across existing data-center infrastructure. “The combination of CXL 3.2 MXC with DDR5 memory technology offers data center customers a solution that balances performance and capacity,” Jangseok Choi, Vice President of Memory Product Planning at Samsung Electronics, said. Montage says it is also offering a software development kit (SDK) and testing tools to help hardware manufacturers evaluate compatibility and integrate the controller into future products. The MXC controller is still in the trial production stage, so its real-world impact will depend on broader industry adoption and further validation. Still, it highlights a growing shift in computing, which is that future AI performance will depend not only on faster processors but also on smarter ways of managing memory. If technologies like CXL 3.2 become widely adopted, future data centers could treat memory as a shared resource instead of a fixed component inside every server, allowing AI systems to scale more efficiently while making better use of existing hardware.Recommended ArticlesGet the latest in engineering, tech, space & science - delivered daily to your inbox.Rupendra Brahambhatt is an experienced writer, researcher, journalist, and filmmaker. With a B.Sc (Hons.) in Science and PGJMC in Mass Communications, he has been actively working with some of the most innovative brands, news agencies, digital magazines, documentary filmmakers, and nonprofits from different parts of the globe. As an author, he works with a vision to bring forward the right information and encourage a constructive mindset among the masses.