Another x86 Advisory From Some Entity Other Than Intel Or AMD

Last October I highlighted an interesting post on the Linux kernel mailing list around an x86 corporate entity other than Intel or AMD that left mysterious intrigue. The developer that detailed those x86 opcode/CPUID/MSR allocations back in July then detailed 16-tile and 32-tile AMX implementations again for something outside the current scope of Intel/AMD processors. Today another message is being relayed from that "corporate entity other than Intel/AMD." The x86 expert Christian Ludloff relayed details today on the Linux kernel mailing list over x86 prefixes on the WBINVD instruction. WBINVD is for Write Back and Invalidate Cache. The new disclosure is over an organizaton other than Intel or AMD using new skip hints with the WBINVD instruction. These skip hints allow for skipping L0i/L1i cache, skip L0d/L1d cache, skip invalidations, and skipping the LLC cache. There are also other new hints defined. "As of 2025, the following are in active use by a corporate entity other than Intel/AMD; therefore they shouldn't be redefined. 0x67 = no CODE hint => skip L0i/L1i cache 0x66 = no DATA hint => skip L0d/L1d cache 0xF3 = no INVD hint => skip invalidations 0xF2 = no LLC hint => skip LLC cache While CODE and DATA hint that the operation should skip code and data caches, LLC hints that the operation should skip a last-level cache, and INVD does remain unchanged. ... In addition the six implementation-specific hints select up to six or 2^6=64 behaviors, depending on the particular processor. 0x26 = ES implementation-specific hint 0x2E = CS implementation-specific hint 0x36 = SS implementation-specific hint 0x3E = DS implementation-specific hint 0x64 = FS implementation-specific hint 0x65 = GS implementation-specific hint One particular implemention might use these to target CODE vs DATA vs STREAMING STORES, as well as cache level L1 vs L2 vs L3. Another particular implementation might use these to target programmable behavior. All ten prefixes can be combined, resulting in an instruction up to 12 bytes long." The message in full can be found on the Linux kernel mailing list. As for who this entity is with these x86 changes, most recently now around WBINVD hints, remains unclear. Making news some weeks ago was a start-up RosaicLabs reportedly receiving access to Intel Atom processor designs. The timing raises the possibility that this entity could be RosaicLabs but it remains to be confirmed.