AMD's 6th Gen EPYC lineup splits four ways — and the power spec changed, too

Published Jul 23, 2026, 1:25 PM EDT His love of PCs and their components was born out of trying to squeeze every ounce of performance out of the family computer. Tinkering with his own build at age 10 turned into building PCs for friends and family, fostering a passion that would ultimately take shape as a career path. Besides being the first call for tech support for those close to him, Ty is a computer science student, with his focus being cloud computing and networking. He also competed in semi-pro Counter-Strike for 8 years, making him intimately familiar with everything to do with peripherals. Sign in to your XDA account Summary AMD has split its 6th Gen EPYC into four families: 9006 SP7, 9006X SP7, 9006 SP8, 9006 LP. Flagship SP7: up to 256 cores/512 threads, 5GHz, PCIe Gen6; 9006X adds triple L3 cache per core. New Default CPU Power metric replaces TDP for total die power; 9956 listed at 400W vs 9965 500W. At its Advancing AI 2026 event in San Francisco, AMD has officially unveiled their 6th Gen EPYC server processors, positioning them as four distinct families rather than the single 256-core flagship that has dominated pre-launch coverage. The EPYC 9006 Series spans the 9006 SP7, 9006 SP8, 9006X SP7 and 9006 LP, each matched to a different job in the data center. The EPYC family grows Four different jobs for four different processors The flagship 6th Gen EPYC 9006 SP7 anchors the top of the stack with up to 256 cores and 512 threads, built for high-density agent sandbox execution. In high-frequency configurations, it doubles as an AI host node, reaching up to 5GHz with best-in-class PCIe Gen 6 connectivity. The 9006X SP7 targets HPC, technical computing and data-intensive workloads, carrying three times the L3 cache per core of the base 9006 SP7, with some variants reaching 5.15GHz. AMD points it at simulation, modeling, in-memory analytics and other memory-sensitive work. The 9006 SP8 covers right-sized deployments with 8- to 128-core options and low-power designs, aimed at edge sites, power-constrained racks, smaller clusters and general-purpose servers. Finally, the fourth processor, the 9006 LP, was previously codenamed Verano. AMD describes it as a purpose-built AI host node CPU using LPDDR memory and enhanced XGMI to keep accelerators fed across dense, accelerator-rich racks. The flagship 9006 SP7 is in production and is expected to begin shipping in Q4 of 2026, while the other three processors are shipping in 2027. Also starting with this generation is a new power metric. AMD has begun to use Default CPU Power rather than its historical TDP reference. The figure reflects total power consumed across the processor's compute and I/O dies at a stated performance target. AMD says both measures can still serve for product comparison and platform planning, but they are not defined identically. In fact, the company's own footnotes list the 6th Gen EPYC 9956 at 400W Default CPU Power against the 5th Gen 9965 at 500W TDP.