A RISC-V Based TEE With AMD Zen 6 CPUs

An interesting technical detail I noticed today from the latest AMD Linux activity is that Zen 6 processors apparently are featuring a RISC-V based Trusted Execution Environment (TEE) where in the past it was an ARM-based core. A little nugget dropped out today in a Git commit with either a new Zen 6 feature or something that wasn't widely reported on for recent Zen 5 processors, but there's now a RISC-V-based TEE with Zen 6 CPUs at least. I haven't been able to find any other references to a RISC-V TEE/core implementation with AMD EPYC/Ryzen processors, but a commit today to linux-firmware.git makes mention of a RISC-V based TEE for Family 1Ah M80h as the upcoming AMD Ryzen Zen 6 client processors: "amd_pmf: Add AMD PMF TA Firmware v4 for 1AH_M80H This adds the PMF TA FW v4 for the 1AH_M80H platform. The TA now runs on the RISC-V based TEE, uses a larger shared memory layout and supports an extended set of policy conditions, including up to 20 custom BIOS inputs." A RISC-V based TEE. Traditionally the AMD Secure Processor / Platform Security Processor (PSP) was based on the Arm Cortex-A5 core with Arm TrustZone technology. Now seemingly new for next-gen Ryzen processors or otherwise just never mentioned for existing SoCs/APUs is a RISC-V based Trusted Execution Environment. In regards to today's firmware drop, it's for the AMD Platform Management Framework (PMF) Trusted Application (TA) for managing power, thermal, and system behavior. Great seeing the AMD Ryzen Zen 6 work getting squared away ahead of the products officially launching.